(1) Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device including a redundancy decoder circuit.
(2) Description of the Prior Art
A recent trend in semiconductor memory devices is for higher integration. Along with this trend, it has become increasingly uneconomical to have to discard an entire memory due to, for example, a defect in a bit memory cell among the large number of memory cells in the device. Thus, in addition to the memory cell array, a one-bit redundancy memory is usually provided. When an address input specifies a defective memory cell, an address jump to the redundancy bit occurs. Therefore, although the memory cell array includes a defective memory cell, it can be used as a normal memory. A decoder circuit is useful for switching the address to the redundancy bit.
Various types of decoder circuits have been put into practical use, such as decoder circuits utilizing fuses or read only memories (ROM). The fuses are suitably fused or the content of the ROMs is suitably determined in such a manner as to change the output of the decoder circuit to logic "H" (high) only when an address corresponding to just the redundancy bit cell is received.
The redundancy decoder circuit to which the present invention is concerned does not utilize a fuse or ROM, but a floating-gate-avalanche-injection metal-oxide semiconductor (FAMOS) transistor. A FAMOS transistor is preferably used for a redundancy decoder circuit when a memory is fabricated as an erasable programmable read only memory (EPROM), in view of the use of common transistor elements for the EPROM and redundancy decoder circuit. This is because an EPROM is usually composed of FAMOS transistors.
A FAMOS transistor type redundancy decoder circuit has not yet been marketed commercially, however, it should come into practical use in the future.